1. Field of the Invention
The present invention relates generally to the design of a superscalar microprocessor and, more particularly, to a system and method for handling load and store operations in a microprocessor that executes instructions out-of-order.
2. Discussion of Related Art
A major consideration in a superscalar Reduced Instruction Set Computer (RISC) processor is how to execute multiple instructions in parallel and out-of-order, without incurring data errors due to dependencies inherent in such execution. The simplest instruction issue policy for RISC processors, is to issue instructions in exact program order (in-order issue) and to write the results in the same order (in-order completion).
Out-of-order completion is more complex than in-order completion, and improves performance of superscalar processors for the same types of operations. For instance, out-of-order completion is used to improve performance of long-latency operations such as loads or floating point operations. Any number of instructions are allowed to be in execution in the functional units, up to the total number of pipeline stages in all functional units. Instructions may complete out of order, because instruction issuing is not stalled when a functional unit takes more than one cycle to compute a result. Consequently, a functional unit may complete an instruction after subsequent instructions already have completed.
Consider the following code sequence where xe2x80x9clopxe2x80x9d is an operation, xe2x80x9cRnxe2x80x9d represents a numbered register, and xe2x80x9c:=xe2x80x9d represents assignment:
R3 := R3 op R5 (1)
R4 := R3+1 (2)
R3 := R5+1 (3)
R7 := R3 op R4 (4)
Here, the assignment of the first instruction cannot be completed after the assignment of the third instruction, even though instructions may in general complete out of order. Completing the first and third instructions out of order would leave an odd, incorrect value in register R3, possibly causing, for example, the fourth instruction to receive an incorrect operand value. The result of the third instruction has an xe2x80x9coutput dependencyxe2x80x9d on the first instruction and the third instruction must complete after the first instruction to produce the correct output values of this code sequence. Thus, issuing of the third instruction must be stalled if its result might later be overwritten by an older instruction which takes longer to compute.
Out-of-order completion yields higher performance, but requires more hardware, namely data dependency logic. Data dependency logic is more complex with out-of-order completion, because this logic checks data dependencies between decoded instructions and all instructions in all pipeline stages. Hardware must also ensure that the results are written in the correct order. In contrast, with in-order completion the dependency logic checks data dependencies between decoded instructions and the few instructions in execution, and results are naturally written in the correct order. Out-of-order completion also creates a need for functional units to arbitrate for result busses and register-file write ports, because there probably are not enough of these to satisfy all instructions that can complete simultaneously.
Moreover, out-of-order completion makes it more difficult to deal with instruction exceptions. An instruction creates an exception when under a given condition, the instruction cannot be properly executed by hardware alone.
In-order issue processors stop decoding instructions whenever a decoded instruction creates a resource conflict or has a true dependency or an output dependency on an uncompleted instruction. The processor is thus not able to look ahead beyond the instructions with the conflict or dependency, even though one or more subsequent instructions might be executable. A conventional solution is to isolate the decoder from the execution stage, so that it continues to decode instructions regardless of whether they could be executed immediately. This isolation is accomplished by providing a buffer (called an xe2x80x9cinstruction windowxe2x80x9d) between the decode and instruction stages.
For look-ahead, the processor decodes instructions and places them into the instruction window as long as there is room in the window, and, at the same time, examines instructions in the window to find instructions that may be executed (i.e., instructions that do not have resource conflicts or dependencies). The instruction window provides a pool of instructions, thus giving the processor a look-ahead ability that is limited by the size of the window and the capability of the processor""s Instruction Fetch Unit (IFU). This permits issuing of instructions out of order because instructions may be issued from the window with little regard for their original program order. The only constraints on the instruction issuer are those required to ensure that the program behaves correctly.
The issue constraints on any particular instruction are mostly the same as with in-order issue: an instruction is issued when it is free of resource conflicts and dependencies. Out-of-order issue gives the processor a larger set of instructions available for issue, improving its chances of finding instructions to execute concurrently. However, the capability to issue instructions out of order introduces an additional issue constraint, much as the capability to complete instructions out of order introduced the constraint of output dependencies.
To understand this, again consider the above example code sequence. The assignment of the third instruction cannot be completed until the second instruction begins execution. Otherwise, the third instruction might incorrectly overwrite the first operand of the second instruction. The result of the third instruction is said to have an xe2x80x9canti-dependencyxe2x80x9d on the first input operand of the second instruction. The term anti-dependency refers to the fact that the constraint is similar to that of true dependencies, except reversed. Instead of the first instruction producing a value that the second uses, the second instruction produces a value that destroys a value that the first one uses. To prevent this, the processor must not issue the third instruction until after the second one begins. Because the second instruction depends on the first, the third instruction also must wait for the first to complete, even though the third instruction is otherwise independent.
Anti-dependencies are mainly of concern when instructions can issue out of order. An input operand of a stalled instruction can be destroyed by a subsequent instruction during normal operation. However, in scalar processors, instruction exceptions are sometimes handled by correcting the exceptional condition, then retrying the problematic instruction. If this instruction completed out of order, it is possible that, when it is retried, its input operands have been overwritten by subsequent instructions. This problem cannot occur in a processor that supports precise interrupts. The solution may require that the processor maintain copies of instruction operands to allow restart.
Two typical operations performed by program instructions are load and store operations. Generally, load and store operations read and modify memory locations, respectively. As with other program instructions, loads and stores can be executed out of order. Even though loads and stores can be decoded at the same time, only one load or store is conventionally issued per cycle. A load is typically given priority over a store to use the data-cache, because the load is likely to produce a value that the processor needs to proceed with computation. If a store conflicts with a load for the data-cache, the store is typically held in a store buffer until the store can be performed. Furthermore, a store is conventionally performed in program-sequential order with respect to other stores, and is performed only after all previous instructions, including loads, have completed. This preserves the processor""s in-order state in the data-cache, because cache updates are not performed until it is absolutely correct to do so. The store buffer aids in keeping stores in the correct order and in deferring the completion of a store until previous instructions have completed.
Because stores are held until the completion of all previous instructions, and because loads produce values needed for computation in the processor, keeping loads in program order with respect to stores has significant negative impact on performance. If a load waits until all preceding stores complete, and therefore waits until all instruction preceding the most recent store complete, then all instructions following the load that depend on the load data also wait. To avoid this performance problem, a load is allowed to bypass preceding stores that are waiting in the store buffer, and the load data is allowed to be used in subsequent computation.
When a load can bypass previous stores, the load may need to obtain data from a previous store that has not yet been performed. The processor checks for a true dependency that a load may have on a previous store by comparing a virtual memory address of the load against a virtual memory addresses of all previous, uncompleted stores (virtual addresses are addresses computed directly by instructions, before address translation by a memory-management unit has been applied). For this discussion, it is assumed that there is a unique mapping for each virtual address, so that it is not possible for two different virtual addresses to access the same physical location. With this assumption, virtual-address comparisons detect all dependencies between physical memory locations. A load has a true dependency on a store if the load address matches the address of a previous store, or if the address of any previous store is not yet computed (in this case, the dependency cannot be detected, so the dependency is usually assumed to exist). If a load is dependent on a store, the load cannot be satisfied by the data-cache, because the data-cache does not have the correct value. If the valid address of a store matches the address of a subsequent load, the load is satisfied directly from the store bufferxe2x80x94once the store data is validxe2x80x94rather than waiting for the store to complete.
As the foregoing discussion implies, loads and stores are performed in a manner that avoids anti- and output dependencies on memory locations. Loads can bypass previous stores, but a store cannot bypass previous loads, so there can be no antidependencies between loads and stores. A store is conventionally issued in program order with respect to other stores, so there can be no output dependencies between stores.
Conventionally, loads are performed at the data cache in program order with respect to other loads. Those skilled in the art have thought that there was little or no performance advantage in allowing loads to be performed out of order, because the data supplied to the processor by older loads is more likely to be needed in computation than the data supplied by new loads.
A more detailed description of some of the concepts discussed above is found in a number of references, including John L. Hennessy et al., Computer Architecturexe2x80x94A Quantitative Approachxe2x80x9d (Morgan Kaufmann Publishers, Inc., San Mateo, Calif., 1990) and Mike Johnson, Superscalar Microprocessor Design (Prentice-Hall, Inc., Englewood Cliffs, N.J., (specifically chapter 8, parts of which have been reproduced above) 1991) which are both incorporated by reference in their entirety.
The present invention provides a system for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. The present invention provides a microprocessor system for executing a program stream which includes an instruction fetch unit for fetching instructions from an instruction store and for providing a predetermined plurality of the instructions to an instruction buffer. It further includes an instruction execution unit, coupled to the instruction fetch unit, for instruction executing the plurality of instructions from the instruction buffer in an out-of-order fashion.
The execution unit includes a load/store unit adapted to make load requests to a memory system out-of-order and store requests in-order. Thus, the main purpose of the load/store unit of the present invention is to make load requests out of order whenever feasible to get the load data back to the instruction execution unit as quickly as possible. A load operation can only be performed out-of-order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns eight bytes of unaligned data. The load/store unit aligns the data properly before it is returned to the instruction execution unit (IEU). Thus, the three main tasks of the load/store unit are: (1) handling out-of-order cache requests; (2) detecting address collision; and (3) alignment of data.
The load/store unit includes an address path adapted to manage a plurality of addresses associated with the plurality of instructions being executed and address collision means for detecting and signaling whether address collisions and write pendings exist between each of the plurality of instructions being executed. The load/store unit performs the load requests if no address collisions and no write pendings are detected. The load store unit further comprising a data path for transferring load and/or store data to and from the memory system and the instruction execution unit, the data path configured to align data returned from the memory system to thereby permit data not falling on a cache quad-word boundary to be returned from the memory system to the instruction execution unit in correct alignment.